The present invention relates to a semiconductor device incorporating a nonvolatile memory cell having a floating gate electrode and a control gate electrode and a method for fabricating the same.
In recent years, as the prices of various system units have been reduced and products have been replaced in shorter and shorter cycles, it is increasingly necessary to further reduce the costs and further shorten the development cycle of semiconductor devices. In particular, a semiconductor device (flash-integrated logic LSI), equipped with flash memory and an cutting-edge logic circuit, not only can reduce the costs thanks to the single-chip implementation thereof, but also is expected as a strong candidate device for further shortening the development cycle.
In order to implement dissimilar devices such as flash memories and DRAM/logic circuits on a single chip, the element density should be increased, which in turn requires a fine processing dimension. Important factors in further reducing a processing dimension are the accuracy of a pattern to be formed with respect to a mask pattern and the flatness of a substrate during the formation of a pattern by lithography.
In the improvement of the processing accuracy, technology for forming an element isolation for isolating respective elements plays an important role. Although the element isolation has been formed by a local oxidation of silicon (LOCOS) method, this method has a problem in that phenomenon so-called bird's beak causes a pattern shift, that is, the accuracy of the pattern to be formed with respect to the mask pattern is deteriorated. Thus, in this method, a maximum possible element density has substantially been reached. For this reason, in a memory cell region, the LOCOS method has recently been replaced by a trench isolation method causing no bird's beak phenomenon. Such a flash memory using the trench isolation is disclosed, for example, in Japanese Laid-open Publication No. 3-295276.
FIG. 17 is a cross-sectional view of the semiconductor device disclosed in the above-identified publication. As shown in FIG. 17, a P-type silicon substrate 201 includes a memory cell region Rmemo and a peripheral circuit region Rperi. In FIG. 17, the memory cell region Rmemo is shown as a cross section perpendicular to the gate longitudinal direction, and the peripheral circuit region Rperi is shown as a cross section parallel to the gate longitudinal direction. In the memory cell region Rmemo, a nonvolatile memory cell, including a tunnel oxide film 213a, a floating gate electrode 214, a gate insulator film 215, a control gate electrode 216a, a silicide layer 220a and an impurity layer (not shown) to be source/drain regions, is disposed in an active region surrounded by trench isolations 218. On the other hand, in the peripheral circuit region Rperi, a field effect transistor, including a gate oxide film 213b, a gate electrode 216b, a silicide layer 220b, and an impurity layer 223 to be source/drain regions, is disposed in an active region surrounded by the LOCOS film 212. Furthermore, an interlevel insulator film 222 is deposited on the substrate, and a bit line 224 is formed thereon. This conventional semiconductor device can be formed by the following procedure.
First, the LOCOS film 212 is formed in the peripheral circuit region Rperi, and then the tunnel oxide film 213a and the gate oxide film 213b are formed in the memory cell region Rmemo and the peripheral circuit region Rperi, respectively. Then, the floating gate electrode 214 and the gate oxide film 215 are selectively formed in the memory cell region Rmemo.
Thereafter, a gate electrode film is deposited over the entire surface of the substrate and patterned by lithography and etching, so as to form the control gate electrode 216a in the memory cell region Rmemo and the gate electrode 216b in the peripheral circuit region Rperi, respectively.
Then, element-isolating trenches are formed so as to surround the active region in the memory cell region Rmemo by lithography and etching. An insulator film is deposited over the entire surface of the substrate and then leveled, thereby filling the trenches with the insulator film and forming the trench isolation 218.
Then, after the silicide layers 220a and 220b have been formed on the control gate electrode 216a and the gate electrode 216b, respectively, the interlevel insulator film 222 is deposited on the substrate and the bit line 224 is formed thereon.
By forming the trench isolation 218 in the memory cell region Rmemo in this manner, the accuracy of the pattern to be formed with respect to the mask pattern can be improved and the density of the memory cell region can be increased. Furthermore, the cell area can be reduced by forming the trench isolation 218 to be self-aligned with the floating gate electrode 213a.
Also, a process step of forming the floating gate electrode of the nonvolatile memory cell and the control gate electrode of the field effect transistor of a common conductor film is also employed.
However, this conventional technique has the following problems.
Although the technique can increase the element density of the memory cell region, not only the area of the memory cell region but also the area of the peripheral circuit region need to be reduced in order to increase the density of the entire semiconductor device. The element isolation in the peripheral circuit region may be formed by the trench isolation method instead of the conventional LOCOS method. However, the conventional technique fails to keep the flatness of the entire substrate. More specifically, if the trench isolation structures are to be formed simultaneously in the memory cell region Rmemo and the peripheral circuit region Rperi, then the presence of the floating gate electrode 214 in the memory cell region Rmemo causes a level difference between the control gate electrode 216a in the memory cell region Rmemo and the gate electrode 216b in the peripheral circuit region Rperi, which deteriorates the flatness of the entire substrate.
In short, since it is difficult to simultaneously maintain sufficient accuracy of a pattern to be formed with respect to a mask pattern and sufficient flatness of the substrate, the single-chip implementation of a flash-integrated logic LSI has been hard to realize.